ESD and EOS are among the leading causes of failure in integrated circuits and may occur both during manufacturing and in the field. ESD (Electrostatic Discharge) is an event lasting nano seconds or less, caused by the sudden transfer of charge between two surfaces. Electrical Overstress (EOS), on the other hand, results from a surge of voltage or current that exceeds the maximum ratings of the affected device. Due to this vulnerability, design engineers incorporate ESD protection circuitry within chip designs and add overstress suppressing elements in the PCBAs to protect the ICs. ICs also undergo stringent reliability testing to ensure their robustness against these events. However, when a failure does occur, failure analysis is required to determine the location of the failure and its root cause. This analysis, using various techniques, may identify the failure site often the location of electrically induced physical damage. Determining the root cause however, depends on the type, extent, and location of the observed damage.
In manufacturing, ESD events may occur during handling and testing, involving both humans such as test operators and engineers as well as machines, such as probers and pick and place equipment. Various models are used to simulate ESD events and are applied in reliability ESD stress testing. The most commonly used models are the HBM and CDM models. HBM, which stands for Human Body Model, simulates ESD events involving humans as the charged surface transferring electrostatic energy to electronic chips. In this model, the human is represented as a 100pF charged capacitor in series with a 1.5 kΩ resistor, discharging electrostatic energy into an electronic component such as an IC. During an HBM ESD event, a surge of current occurs reaching approximately 0.67 A at 1 kV which then decays over 100+ nanoseconds [1]. This prolonged surge of current may induce physical damage in ICs if it is not properly clamped. The damage typically affects the ESD clamp FETs or diodes, which are designed to shunt this electrostatic energy away from sensitive circuitry redirecting it to the GND or VDD rails. The damage to ESD clamps is primarily caused by thermal runaway. If the HBM ESD event is fast enough, it can bypass the ESD protection circuitry entirely and damage internal components. This often manifests as electromigration type damage in interconnects or junction failures in affected FETs.
The CDM model, on the other hand, simulates ESD events involving electronic components and other surfaces, such as testing and manufacturing equipment like probers, testers, and pick and place machines. The CDM model simulates a sudden discharge between the charged IC device which is modeled as a capacitor, inductor, and resistor in series and a lower potential or ground (GND) surface, resulting in a sub-nanosecond fast transient of current reaching up to tens of amperes [2]. Under certain conditions, this electrostatic energy may dissipate into the internal device circuitry, resulting in polysilicon puncture or oxide breakdown type damage, which may occur in FETs and integrated capacitors (MIM, MOM, and MOS). This damage is miniscule and sometimes undetectable with optical or LSM inspection and may require SEM imaging to visualize.
As for EOS, it occurs when an IC is exposed to high voltages and currents that exceed its absolute maximum ratings for an extended duration, usually lasting from microseconds to milliseconds. Due to the prolonged nature of EOS events, the damage induced inside ICs is often quite catastrophic. This damage is typically caused by electromigration and thermal runaway, resulting in significant melting of metal lines, polysilicon, and active circuitry FETs. Depending on its extent and severity, EOS induced physical damage may be visible to the naked eye or under high power microscopes. If the damage is not optically visible from the front side of the IC, it can be detected through the backside of ICs utilizing Laser Scanning Microscopy (LSM).
References:
[1] EOS/ESD Association, Inc., JEDEC Solid State Technology Association, “ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level,” ANSI/ESDA/JEDEC JS-001-2017, May 2017.[2] Electro Static Discharge Association, JEDEC Solid State Technology Association, “ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) – Device Level,” ANSI/ESDA/JEDEC JS-002-2018, Dec 2018.
